1. Field of the Invention
The present invention generally relates to computer logic system testing and, more particularly, to the testing of path delays through a functional organization of logic utilized in, for example, large, complex digital computer systems implemented with high density, large scale integrated circuits. The invention facilitates the analysis of dynamic clock system performance in large, complex digital computer systems.
2. Description of the Prior Art
Propagation delay in large scale computing systems has been, from the beginning, a factor in the performance of those systems. Therefore, it has been routine to test the delay paths between modules of a computing system in order to adjust and fine tune the system for optimum performance. Such measurements were relatively easy to perform when the components of the system were discrete and test pads could be designed into the circuitry. For example, accessible paths could be timed physically using oscilloscopes and probes. However, the capacitance from the probes adversely affects the delays being measured, thereby producing significant error in the measurements themselves. As the cycle times of these large systems decrease, the adverse effects of these probes continue to grow.
With the advent of large scale circuit integration, the problem of measuring path delays has become increasingly difficult. In current technology, timing of these paths using measurement probes is virtually impossible, given the density of the logic and the extremely limited physical access to probing points. This will only become more difficult as chip and component densities increase. Performing this task with an oscilloscope and probes is no longer feasible.
Another prior art method for finding path delay is with specially written software which estimates the delays of the circuits in a given logic path. This method has a significant drawback since it is only an estimation of the delay. For instance, the delays used by the program may have been incorrectly coded or the hardware built may not actually reflect the delay values used by the program.
Hand calculations are also used to find the delay of logic paths. This method is also susceptible to error since there may exist little or no correlation between the mathematical equations used in the calculations and the physical delays of the actual hardware.
Each of these prior art measurement techniques introduces some degree of inaccuracy and lack of confidence in the results. The prior art methods are also very time consuming.
An early solution to the problem of measuring the propagation delay of a functional logic system was provided by E. B. Eichelberger in U.S. Pat. No. 3,784,907. The logical units testable according to the Eichelberger method employ clocked d.c. latches for all internal storage circuitry in the arithmetic/logical units (ALUs) of the computing system. This latch circuitry is partitioned along with associated combinatorial logic networks and arranged in sets. The plural clock trains are synchronous but non-overlapping and independent. The storage circuitry has the capability for performing scan-in/scan-out operations independently of the system input/output controls. Using this scan capability, the Eichelberger method provides for the state of the storage circuitry to be preconditioned and independent of its prior history. Selected propagation paths through the system circuitry are sensitized by test patterns from an automatic test generator. By altering selected inputs and cycling controls applied to the networks of combinatorial logic and their respective associated storage circuitry, propagation delay indications through selected paths are obtained to determine the status of these path delays through the logic system.
U.S. Pat. No. 4,063,080 to Eichelberger et al. teaches an organization of logic and arrays which is oriented towards testing of propagation delays. This organization employs clocked d.c. latches for all internal circuitry in the arithmetic, logical and control units of a computing system. The latch circuitry is partitioned along with associated combinatorial logic networks and arrays and arranged in sets. The sets of latch circuitry are coupled through combinatorial logic and arrays to other sets of latches that are controlled by system clock trains. Additional circuitry allows for all latches to become shift register latches and, by external control, to be connected into one or more shift registers. These shift registers are activated by clocks independent of the system clocks and, when the system clocks are deactivated, all sets of latches are isolated from each other. The effect of this isolation, coupled with the scan-in/scan-out capability is to reduce all sequential circuitry arrays fed by and, in turn, feeding combinatorial circuitry for purposes of measuring propagation delays through selected paths.
In addition to measuring propagation delay in large scale computing systems, a significant amount of time is spent analyzing the performance of the clock distribution system since it directly impacts the performance of a machine. The reason for this is that the performance of clocking systems in large scale systems directly impacts the overall performance of those systems since clock skew subtracts from the actual cycle time of a machine. For example, a machine theoretically running at a cycle time of seventeen nanoseconds actually has less than seventeen nanoseconds for register-to-register transfers. In fact, it can be considerably less than seventeen nanoseconds for several reasons, one of which is system clock skew. Clock skew is defined as the relative difference between any two different clock edges. The clock edges being compared could be from trigger clocks and latch clocks (in an LSSD environment), trigger clocks and array clocks, or the like.
In the past, clock system analysis consisted of clock delay measurements and comparisons which were extremely time consuming. An oscilloscope and associated measurement equipment were necessary to obtain the empirical results. By its very nature, this analysis was constrained by physical access to various points of interest in the clocking structure. Moreover, the loading effect of the oscilloscope probes on the physical access points contributed a relatively unknown amount of capacitance to the clock network making the resultant measurements less accurate. Additional assumptions were required to account for the loading introduced by the external measurement equipment.
As a practical matter, there often are hundreds of measurement points and it is impractical, due to constraints of time, to make measurements at all measurement points provided in the system. Therefore, a procedure has developed where measurements are done on a sample of the hardware, and conclusions regarding the overall clock system performance across all systems and modules are made based on this sample.